Conventional integrated circuits that include randomly accessible memory, such circuits including both memory circuits such as static random access memories (sRAMs), and also microprocessors, logic arrays, and other very large scale integrated (VLSI) circuits having memory embedded therein, generally include an array or arrays of memory cells arranged in rows and columns. A portion of the memory address selects a row of memory cells, and a portion of the memory address selects one or more of the memory cells in the selected row for access thereof, either for reading data from or writing data to the addressed location.
Referring to FIG. 1, a conventional static RAM cell 26 in such an arrangement is illustrated. Cell 26 is constructed as a pair of cross-coupled inverters with resistor pull-ups. N-channel pull-down transistor 30a has its source-to-drain path connected between node SA and ground, and n-channel pull-down transistor 30b has its source-to-drain path connected between node SB and ground. Load devices 32a and 32b are connected between the power supply node V.sub.cc, and nodes SA and SB, respectively. In the example of FIG. 1, load devices 32 are polysilicon resistors which provide extremely high resistance, for example on the order of 5 Teraohms. An example of such resistors and their construction is described in U.S. Pat. No. 4,251,876, incorporated herein by this reference. While FIG. 1 shows load devices 32a and 32b as resistors, it should be noted that conventional sRAM cells 26 are also constructed as full complementary metal-oxide-semiconductor (CMOS) cells, where load devices 32 are p-channel transistors having their source-to-drain paths connected between V.sub.cc and the cross-coupled nodes SA and SB, respectively, and their gates connected to the cross-coupled node opposite from their respective drains. It should be noted that the effects described hereinbelow have also been observed in such full CMOS cells.
Memory cell 26 is connected to complementary bit lines BL and BL.sub.-- by way of pass transistors 34, each of which are controlled by row line RL. Row line RL is driven, as is conventional in the art, by a row decoder which decodes the portion of the memory address for selecting a row in the memory device, and which energizes one of the row lines RL for the device responsive thereto. Pass transistors 34 thus place the selected memory cells in communication with the remainder of the memory device via bit lines BL and BL.sub.--.
In operation, memory cell 26 will be in one of two states. A first state is where transistor 30a is on, so that node SA is pulled to a voltage at or near ground; in this state, since node SA is at a low voltage, transistor 30b is off, and load device 32b pulls node SB to a voltage at or near V.sub.cc. The second state is of course the opposite condition, where transistor 30b is on, so that node SB is near ground, with transistor 30a off so that node SA is near V.sub.cc. During such time as pass transistors 34 are energized by row line RL, the stored data state at nodes SA and SB may be communicated to, or set by, conventional sense amplifiers and write circuitry via bit lines BL and BL.sub.--.
In the physical construction of memory cells such as cell 26 of FIG. 1, one of the two stored states will necessarily have a higher holding, or leakage, current than the other. Where the load devices 32 are extremely high resistance polysilicon resistors as in the case of FIG. 1, the difference in current will likely be due to differences in the off-state leakage currents for the transistors 30. For example, a small defect may be present for one of the transistors 30 which can cause junction leakage from the drain of a transistor 30 to the substrate. In addition, a defect may be present in the channel of one of transistors 30 which reduces its channel length, such that its sub-threshold source-drain leakage is much increased over nominal values. Each of these leakage mechanisms will tend to cause conduction from the drain node when the transistor 30 is in its off state. Accordingly, if one of the transistors 30 has such a defect, the standby current will be significantly greater for the state where the leaky transistor 30 is off than for the state where the leaky transistor 30 is on (and where the less leaky transistor 30 is off), perhaps by several orders of magnitude. It should be noted that the defect need not be of such magnitude as to cause a loss of functionality in order for a significant difference in the leakage current to be present for a memory cell. Indeed, in the manufacture of such memories, if defects are observed which cause non-functionality due to junction or source-drain leakage in one or more memory cells for some memories on the wafer, it is quite likely that smaller defects which are capable of causing significant leakage current will be present in other, functional, memories on the same wafer.
Other factors may also cause differences in the leakage current between the two potential data states. For example, defects in the resistors, or design and layout differences in the resistors, either of which affect such characteristics as their width, length, and doping concentration, and such other factors as the resistance of metal contacts to the polysilicon resistors, may also cause higher leakage current for one of the two data states. In addition, design and layout differences between the pull-down devices, or other types of defects in these transistors, will also affect the leakage current in the stored states. It should be noted that for other types of cells, including full CMOS cells, and also dual-port memory cells and FIFO cells, similar differences in the leakage currents for the two states will also be present.
An important consideration in static RAMs, dual-port RAMs, FIFOs, logic circuits with embedded memories, and in other integrated circuits which contain static memory cells such as memory cell 26 of FIG. 1, is the standby current drawn by the memory array. This is an especially important consideration for those circuits which are intended to be used in a battery back-up mode, i.e., where the stored data is to be maintained for long periods of time solely by the application of a bias voltage to the V.sub.cc power supply terminal from a battery. An example of a memory having battery backup capability is described in U.S. Pat. No. 4,288,865, incorporated herein by this reference. Accordingly, a low standby current is desired for such memories, and the manufacturers of circuits containing such memories generally perform manufacturing tests for each circuit in order to guarantee that the standby current specifications are met.
Since each memory cell 26 will have one state in which the leakage current is larger than for the other state, a distribution of standby current exists based upon the percentage of cells in the circuit which are in its high current state. FIG. 2 illustrates a distribution of standby current I.sub.sb versus the percentage of memory cells in a given circuit which are in the high current state. As is evident from FIG. 2, a minimum standby current level I.sub.sbmin exists where all memory cells are storing their low current state, and a maximum standby current level I.sub.sbmax exists where all memory cells are storing their high current state. It should be noted that the difference between I.sub.sbmin and I.sub.sbmax may be small for those memories in the manufacturing population which do not have cells with defects causing significant leakage in one data state. However, it has been observed that the manufacturing population of memory devices will generally include devices which exhibit data state dependency of standby current caused by defects of non-killing size which result in junction or sub-threshold source-drain leakage; the difference between I.sub.sbmin and I.sub.sbmax for such devices can be quite large. The worst case standby current level I.sub.sbmax for a given device must be below the standby current specification limit in order for it to meet all specifications.
Due to the defect driven nature of this leakage mechanism, it is not predictable which state (i.e., node SA high or node SB high) will be the high standby current state for a particular memory cell 26. This is because, for best performance, each memory cell 26 is designed to be as balanced as possible, so that the writing of data in one state does not take longer than the writing of data in the other state. Accordingly, since large changes in leakage current result from manufacturing defects, the data state which is the high current state will be random from cell to cell. Due to the random nature of these defects, the thorough and accurate measurement of I.sub.sbmax for an n-bit memory requires the measurement of I.sub.sbmax for 2.sup.n data patterns, so that the pattern of data which has the highest standby current I.sub.sbmax is found and compared to the specification limit. Such testing is of course impracticable in high volume manufacturing testing.
Prior test methods have included the measurement of I.sub.sb for a small number of stored data patterns. For example, the memory may be written with all zeroes, all ones, checkerboard, and checkerboard complement, with the standby current I.sub.sb measured for each. Such testing will generally ensure that the standby current I.sub.sb has been measured, at least once, approximately near where 50% of the cells are in the high leakage current state, so that a standby current near the value I.sub.sb50 is measured. Especially considering the random location and size of defects which affect the standby current, such a test will, at best, detect only those memories in the manufacturing population which have a high degree of defect dependent standby current. Accordingly, some circuits would not meet the standby current specification for their worst case, but will improperly pass conventional standby current tests.
Another important test for memories such as static RAMs is a disturb test. In a first type of disturb test conventionally performed on static RAMs, the memory cell under test is written to one state, followed by repeated reads of this cell. In a static RAM memory cell, especially where load devices 32 are high resistance value resistors, the coupling of voltages from the bit lines BL and BL.sub.-- through the pass gates to the nodes SA and SB, as occurs in read operations, can cause weak cells to be upset. In this test, after repeated read operations to the memory cell, its contents are compared against the value written in the first cycle, to determine if the repeated reads have upset the memory cell.
A second type of well-known static RAM disturb test includes repeated read operations to neighboring cells in an adjacent row, particularly in memory arrays where the ground connection may not be directly made for each memory cell. Local voltage drops in the path between the source of transistors 30 and ground due to the conduction of accessed memory cells can also cause upset of weak memory cells. Accordingly, the disturb test may be performed by writing a known state into a memory cell, repeatedly accessing its neighbors in an adjacent row, followed by reading the cell under test to determine if it has retained its written data state.
As described above relative to FIG. 1, the two data states available for a conventional sRAM memory cell 26 may not be symmetric, especially in the presence of a defect. If, for example, transistor 30b is defective such that its drain node (node SB) is leaking either to the substrate node of transistor 30b (at zero volts or below) or to the source of transistor 30b (at ground), the voltage at node SB will be pulled low by such leakage, which tends to turn off transistor 30a. Of course, if such leakage is excessive, the memory cell will not be able to be written to the data state where node SB is high. However, if the defect is only of such a size that the leakage is moderate, and if the memory cell is set to the state where transistor 30a is on and transistor 30b is off, the leakage of transistor 30b will cause the gate voltage at transistor 30a to be closer to the off state than normal. This will cause node SA, at the drain of transistor 30a, to be at a higher voltage than normal (i.e., closer to the threshold voltage of transistor 30b). With the gate of the off transistor 30b closer to its threshold voltage than normal, it is easier for noise, for example from bit line BL through pass transistor 34, to turn on transistor 30b and reset the memory cell state. The worst case for the disturb test thus corresponds to the data state where the leaky one of the transistors 30 is off, which also corresponds to the high standby current data state as discussed above.
As described above, it is not feasible to test each of the possible data patterns in a memory in order to ensure that the worst case condition is used in the disturb test, especially considering that the less stable state depends, in many cases, on the presence of random defects. This becomes even less feasible as the memory size increases, such as to 1 Mbit or larger. Accordingly, the worst case disturb test may not be tested for a particular memory device, allowing weak devices to pass the manufacturing tests.
Similarly, for purposes of measuring the soft error rate of such memories over time, the least stable condition is where all memory cells are in their high standby current data state. As soft error rate characterization is generally performed over relatively long periods of time, whether using an accelerated alpha particle source or in ambient system conditions, providing 2.sup.n data patterns for such testing results in little time being spent in the worst case condition during the performance of the test.
It is therefore an object of this invention to provide an improved method of testing an integrated circuit including a memory array.
It is a further object of this invention to provide such a method which may be quickly performed in a special test mode.
It is a further object of this invention to provide a circuit having capability for such testing.
It is a further object of this invention to provide such a circuit and method which may be used to establish the worst case condition for the measurement of the standby current of a memory.
It is a further object of this invention to provide such a circuit and method which may be used to establish the worst case condition for disturb testing.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to this specification together with the drawings.